The present invention relates to semiconductor features, and in particular to an interconnect for integrated circuits.
Reduction of integrated circuit feature size has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines. As a result, capacitance has increased between such conductive portions, resulting in RC (resistance×conductance) delay time and crosstalk effect. One proposed approach to this problem is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with other insulation material having a lower dielectric constant, to thereby lower capacitance.
Unfortunately, low-k dielectric materials have various problems that make integration into existing integrated circuit structures and processes difficult. Compared to conventional dielectric materials used in semiconductor fabrication, most low-k materials typically present characteristics such as high tensile stress. Such high tensile stresses accumulating in a semiconductor structure can lead to bowing or deformation, cracking, peeling, or formation of voids of a film therein, which can damage or destroy an interconnect that includes the film, affecting reliability of a resulting integrated circuit.